Designing and Programming CPLDs
CPLD stands for Complex Programmable Logic Device. It is a digital logic IC which can be programmed with custom internal logic circuits. Useful for low to medium complexity when you need high speed.
CPLDs: Overwiew and Purpose
CPLDs are programmable logic devices and can be programmed to be e.g. a latch, a counter, a shift register or a fancy combination of things like that. However, don't come up with too large plans since the amount of logic you can put into a CPLD is quite limited.
CPLDs don't replace microcontrollers and vice versa; in fact, they complement one another very well: CPLDs are good if you need speed as long as the complexity of the task is limited. In contrast, microcontrollers can do lots of fancy things but at slower speed.
For example, consider a 3-channel event counter: This can easily can be implemented using an AVR microcontroller connected to a XC9572 CPLD. The CPLD just holds 3 separate 16-bit counters and some additional logic so that the microcontroller can read back the result from the counters. The overflow pins from the counters are connected to the microcontroller as well, so that the bits 16..31 of the result are countet by the controller. Now, the microcontroller has all the user interface and display routines programmed in, possibly even an USB connection or a constantly updated LED display (too complex for CPLD). The CPLD in turn does the fast counting part allowing all three inputs to be clocked at up to 100 MHz (impossible with AVR microcontroller).
Designing (with) CPLDs
Designing the internal contents of a CPLD has some similarities to writing firmware for a microcontroller: You specify the content in some sort of language (e.g. as VHDL or as schematic), this "source" is then compiled for the CPLD in question and finally downloaded onto the chip using the JTAG port.
The precise way to do these steps depends on the applied CPLD and the tools offered by the manufacturer. I recommend Xilinx CPLDs (XC9500XL series for low price and and CoolRunner-II series for even more speed) since Xilinx offers a free and full-featured development suite called ISE WebPACK which is available both for Linux and for Windows! You need to register (name and email suffice) before the download and it's really huge, so be prepared to download more than 1Gb!
ISE WebPACK is a professional integrated development environment for CPLDs and FPGAs and not only allows you to design the content of the programmable logic device but also to simulate the logic behavior including the expected delays occuring on the chip. This page is not meant to be a manual for Xilinx ISE WebPACK but here are short howto-like instructions for certain steps I decided to put here for some reason.
Programming the CPLD
When using an integrated development environment like ISE WebPACK, you can directly communicate with the programmable logic device provided you buy one of the supported download cables. These usually connect to the host computer's parallel port or a USB port and cost around 100 Euros or so.
If you don't want to spend that money (which is the way I decided to go), you can create an SVF file which basically contains the waveforms to be sent out over the JTAG port in order to program the logic device (CPLD). Such an SVF file can be downloaded onto the logic device e.g. via my self-designed USB-AtmelPrg download cable via its dedicated software tool:
usb-atmelprg> svfprog counter.svf Programming SVF file: 186450 bits in 808 blocks... Elapsed: 7927 msec (slept 2761 msec); rate: 9.810644 msec/pack usb-atmelprg> _
That's all (assuming that your SVF file was called counter.svf). Really simple, isn't it? Now, disconnect the CPLD and test it. (More information on USB-AtmelPrg's JTAG port.)