Consider you finished off the CPLD/FPGA design and finally want to get
it onto the programmable logic IC by means of a download cable which
can execute SVF files
(like my USB-AtmelPrg).
So, here is how to create an SVF file in Xilinx ISE WebPACK e.g. for
an XC9572XL CPLD:
Select Configure Device (iMPACT) which is visible when expanding the
level Generate Programming File invoked before and double-click or
use again Run from the context menu. This will bring up iMPACT after
Select Prepare a Boundary-Scan File and format SVF:
Now, a file selection box will pop up where you should enter the file
name of the SVF file to be generated. Enter test.svf and
press the return key.
iMPACT will inform you that all operations are now directed to a file,
so press OK after having read the box.
Now, a file selection dialog will show up allowing you to select the
design file to be loaded onto the programmable logic chip; in our case
this is main.jed.
The SVF file created in the following steps will contain all the actions
we perform now in the order we do them.
So, select the context menu of the IC symbol to get a list of
available commands; this should look as shown below:
In this order, select the following commands:
Erase... to erase the CPLD (or better: to write the erase commands
to the SVF file). (Say OK to the next box, of course.)
Note that may not even be necessary since you can activate erasing when
programming as well. But let's be sure this time...
You can also first call Get Device ID but this is always done as
first step when programming so it is actually not needed.
Program... to actually program the previously selected JEDEC file
onto the XC9572XL CPLD. Make sure Verify is activated so that errors
at programming time can be detected. Press OK.
That's all. Exit iMPACT now. We have the SVF file ready.
Now, it's merely about downloading it
(e.g. via the command svfprog of USB-AtmelPrg's